/*
 * Copyright (C) STMicroelectronics Ltd. 2007.
 *
 * All rights reserved.
 */

/*
 * This is derived from STMicroelectronics gnu toolchain example:
 *   sh-superh-elf/examples/bare/sh4reg/sti7200reg.h
 */


#ifndef __STX7200REG_H
#define __STX7200REG_H

#include "sh4regtype.h"

/*----------------------------------------------------------------------------*/

/*
 * Peripheral versions
 */

#ifndef ST40_LMIGP_VERSION
#define ST40_LMIGP_VERSION 1
#endif

/*----------------------------------------------------------------------------*/

/*
 * Base addresses for control register banks.
 */

/* Generic SH4 control registers */
#ifndef SH4_TMU_REGS_BASE
#define SH4_TMU_REGS_BASE 0xffd80000
#endif
#ifndef SH4_RTC_REGS_BASE
#define SH4_RTC_REGS_BASE 0xffc80000
#endif

/* Common ST40 control registers */
#ifndef ST40_CPG_REGS_BASE
#define ST40_CPG_REGS_BASE 0xffc00000
#endif
#ifndef ST40_INTC_REGS_BASE
#define ST40_INTC_REGS_BASE 0xffd00000
#endif
#ifndef ST40_SCIF2_REGS_BASE
#define ST40_SCIF2_REGS_BASE 0xffe80000
#endif

#ifndef ST40_ILC_REGS_BASE
#define ST40_ILC_REGS_BASE 0xfd804000
#endif

/* STx7200 control registers */
#ifndef STX7200_SYSCONF_REGS_BASE
#define STX7200_SYSCONF_REGS_BASE 0xfd704000
#endif

#ifndef STX7200_CLOCKGENA_REGS_BASE
#define STX7200_CLOCKGENA_REGS_BASE 0xfd700000
#endif

#ifndef STX7200_CLOCKGENB_REGS_BASE
#define STX7200_CLOCKGENB_REGS_BASE (STX7200_CLOCKGENA_REGS_BASE + 0x1000)
#endif

#ifndef STX7200_CLOCKGENC_REGS_BASE
#define STX7200_CLOCKGENC_REGS_BASE (STX7200_CLOCKGENA_REGS_BASE + 0x2000)
#endif

#ifndef STX7200_STBUS_NODE00_REGS_BASE
#define STX7200_STBUS_NODE00_REGS_BASE 0xfdc05000
#endif
#ifndef STX7200_STBUS_NODE01_REGS_BASE
#define STX7200_STBUS_NODE01_REGS_BASE 0xfdc05c00
#endif
#ifndef STX7200_STBUS_NODE04_REGS_BASE
#define STX7200_STBUS_NODE04_REGS_BASE 0xfdc05600
#endif
#ifndef STX7200_STBUS_NODE08_REGS_BASE
#define STX7200_STBUS_NODE08_REGS_BASE 0xfdc05a00
#endif
#ifndef STX7200_STBUS_NODE09_REGS_BASE
#define STX7200_STBUS_NODE09_REGS_BASE 0xfdc06000
#endif
#ifndef STX7200_STBUS_NODE10_REGS_BASE
#define STX7200_STBUS_NODE10_REGS_BASE 0xfdc06200
#endif
#ifndef STX7200_STBUS_NODE12_REGS_BASE
#define STX7200_STBUS_NODE12_REGS_BASE 0xfdc05800
#endif
#ifndef STX7200_STBUS_NODE13_REGS_BASE
#define STX7200_STBUS_NODE13_REGS_BASE 0xfdc05200
#endif
#ifndef STX7200_STBUS_NODE17_REGS_BASE
#define STX7200_STBUS_NODE17_REGS_BASE 0xfdc05400
#endif
#ifndef STX7200_STBUS_NODE18_REGS_BASE
#define STX7200_STBUS_NODE18_REGS_BASE 0xfdc05e00
#endif
#ifndef STX7200_STBUS_NODE20_REGS_BASE
#define STX7200_STBUS_NODE20_REGS_BASE 0xfdc06400
#endif

/* System Architecture Volume 2: Bus Interfaces */
#ifndef ST40_LMI0_REGS_BASE
#define ST40_LMI0_REGS_BASE 0xfdd18000
#endif
#ifndef ST40_LMI1_REGS_BASE
#define ST40_LMI1_REGS_BASE 0xfdd19000
#endif
#ifndef ST40_EMI_REGS_BASE
#define ST40_EMI_REGS_BASE 0xfdf00000
#endif

/* System Architecture Volume 4: I/O Devices */
#ifndef STX7200_COMMS_BASE
#define STX7200_COMMS_BASE 0xfd000000
#endif

#ifndef ST40_PIO0_REGS_BASE
#define ST40_PIO0_REGS_BASE (STX7200_COMMS_BASE + 0x00020000)
#endif
#ifndef ST40_PIO1_REGS_BASE
#define ST40_PIO1_REGS_BASE (STX7200_COMMS_BASE + 0x00021000)
#endif
#ifndef ST40_PIO2_REGS_BASE
#define ST40_PIO2_REGS_BASE (STX7200_COMMS_BASE + 0x00022000)
#endif
#ifndef ST40_PIO3_REGS_BASE
#define ST40_PIO3_REGS_BASE (STX7200_COMMS_BASE + 0x00023000)
#endif
#ifndef ST40_PIO4_REGS_BASE
#define ST40_PIO4_REGS_BASE (STX7200_COMMS_BASE + 0x00024000)
#endif
#ifndef ST40_PIO5_REGS_BASE
#define ST40_PIO5_REGS_BASE (STX7200_COMMS_BASE + 0x00025000)
#endif
#ifndef ST40_PIO6_REGS_BASE
#define ST40_PIO6_REGS_BASE (STX7200_COMMS_BASE + 0x00026000)
#endif
#ifndef ST40_PIO7_REGS_BASE
#define ST40_PIO7_REGS_BASE (STX7200_COMMS_BASE + 0x00027000)
#endif
#ifndef ST40_ASC0_REGS_BASE
#define ST40_ASC0_REGS_BASE (STX7200_COMMS_BASE + 0x00030000)
#endif
#ifndef ST40_ASC1_REGS_BASE
#define ST40_ASC1_REGS_BASE (STX7200_COMMS_BASE + 0x00031000)
#endif
#ifndef ST40_ASC2_REGS_BASE
#define ST40_ASC2_REGS_BASE (STX7200_COMMS_BASE + 0x00032000)
#endif
#ifndef ST40_ASC3_REGS_BASE
#define ST40_ASC3_REGS_BASE (STX7200_COMMS_BASE + 0x00033000)
#endif
#ifndef ST40_SSC0_REGS_BASE
#define ST40_SSC0_REGS_BASE (STX7200_COMMS_BASE + 0x00040000)
#endif
#ifndef ST40_SSC1_REGS_BASE
#define ST40_SSC1_REGS_BASE (STX7200_COMMS_BASE + 0x00041000)
#endif
#ifndef ST40_SSC2_REGS_BASE
#define ST40_SSC2_REGS_BASE (STX7200_COMMS_BASE + 0x00042000)
#endif
#ifndef ST40_SSC3_REGS_BASE
#define ST40_SSC3_REGS_BASE (STX7200_COMMS_BASE + 0x00043000)
#endif
#ifndef ST40_SSC4_REGS_BASE
#define ST40_SSC4_REGS_BASE (STX7200_COMMS_BASE + 0x00044000)
#endif
#ifndef ST40_MAILBOX0_REGS_BASE
#define ST40_MAILBOX0_REGS_BASE 0xfd800000
#endif
#ifndef ST40_MAILBOX1_REGS_BASE
#define ST40_MAILBOX1_REGS_BASE (ST40_MAILBOX0_REGS_BASE + 0x1000)
#endif
#ifndef ST40_MAILBOX2_REGS_BASE
#define ST40_MAILBOX2_REGS_BASE (ST40_MAILBOX0_REGS_BASE + 0x2000)
#endif
#ifndef ST40_MAILBOX3_REGS_BASE
#define ST40_MAILBOX3_REGS_BASE (ST40_MAILBOX0_REGS_BASE + 0x3000)
#endif

/*----------------------------------------------------------------------------*/

#include "st40reg.h"

/*
 * STx7200 control registers
 */

/* Clock Generator control registers (STx7200 variant) */
#define STX7200_CLOCKGENA_PLL0_CFG		SH4_DWORD_REG(STX7200_CLOCKGENA_REGS_BASE + 0x00)
#define STX7200_CLOCKGENA_PLL1_CFG		SH4_DWORD_REG(STX7200_CLOCKGENA_REGS_BASE + 0x04)
#define STX7200_CLOCKGENA_PLL2_CFG		SH4_DWORD_REG(STX7200_CLOCKGENA_REGS_BASE + 0x08)
#define STX7200_CLOCKGENA_MUX_CFG		SH4_DWORD_REG(STX7200_CLOCKGENA_REGS_BASE + 0x0c)
#define STX7200_CLOCKGENA_DIV_CFG		SH4_DWORD_REG(STX7200_CLOCKGENA_REGS_BASE + 0x10)
#define STX7200_CLOCKGENA_DIV2_CFG		SH4_DWORD_REG(STX7200_CLOCKGENA_REGS_BASE + 0x14)
#define STX7200_CLOCKGENA_CLKOBS_MUX_CFG	SH4_DWORD_REG(STX7200_CLOCKGENA_REGS_BASE + 0x18)
#define STX7200_CLOCKGENA_POWER_CFG		SH4_DWORD_REG(STX7200_CLOCKGENA_REGS_BASE + 0x1c)
#define STX7200_CLOCKGENA_CLKOBS_MAX		SH4_DWORD_REG(STX7200_CLOCKGENA_REGS_BASE + 0x20)
#define STX7200_CLOCKGENA_CLKOBS_RESULT		SH4_DWORD_REG(STX7200_CLOCKGENA_REGS_BASE + 0x24)
#define STX7200_CLOCKGENA_CLKOBS_CTRL		SH4_DWORD_REG(STX7200_CLOCKGENA_REGS_BASE + 0x28)

#define STX7200_CLOCKGENB_FS0_SETUP		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x00)
#define STX7200_CLOCKGENB_FS1_SETUP		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x04)
#define STX7200_CLOCKGENB_FS2_SETUP		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x08)
#define STX7200_CLOCKGENB_FS0_CLK1_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x0c)
#define STX7200_CLOCKGENB_FS0_CLK2_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x10)
#define STX7200_CLOCKGENB_FS0_CLK3_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x14)
#define STX7200_CLOCKGENB_FS0_CLK4_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x18)
#define STX7200_CLOCKGENB_FS1_CLK1_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x1c)
#define STX7200_CLOCKGENB_FS1_CLK2_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x20)
#define STX7200_CLOCKGENB_FS1_CLK3_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x24)
#define STX7200_CLOCKGENB_FS1_CLK4_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x28)
#define STX7200_CLOCKGENB_FS2_CLK1_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x2c)
#define STX7200_CLOCKGENB_FS2_CLK2_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x30)
#define STX7200_CLOCKGENB_FS2_CLK3_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x34)
#define STX7200_CLOCKGENB_FS2_CLK4_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x38)
#define STX7200_CLOCKGENB_PLL0_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x3c)
#define STX7200_CLOCKGENB_CLKRCV_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x40)
#define STX7200_CLOCKGENB_IN_MUX_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x44)
#define STX7200_CLOCKGENB_OUT_MUX_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x48)
#define STX7200_CLOCKGENB_DIV_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x4c)
#define STX7200_CLOCKGENB_DIV2_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x50)
#define STX7200_CLOCKGENB_CLKOBS_MUX_CFG	SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x54)
#define STX7200_CLOCKGENB_POWER_CFG		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x58)
#define STX7200_CLOCKGENB_CLKOBS_MAX		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x5c)
#define STX7200_CLOCKGENB_CLKOBS_RESULT		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x60)
#define STX7200_CLOCKGENB_CLKOBS_CTRL		SH4_DWORD_REG(STX7200_CLOCKGENB_REGS_BASE + 0x64)

/* System configuration registers (STx7200 variant) */
#define STX7200_SYSCONF_DEVICEID_0	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0000)
#define STX7200_SYSCONF_DEVICEID_1	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0004)
#define STX7200_SYSCONF_DEVICEID	SH4_GWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0000)
#define STX7200_SYSCONF_SYS_STA00	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0008)
#define STX7200_SYSCONF_SYS_STA01	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x000c)
#define STX7200_SYSCONF_SYS_STA02	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0010)
#define STX7200_SYSCONF_SYS_STA03	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0014)
#define STX7200_SYSCONF_SYS_STA04	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0018)
#define STX7200_SYSCONF_SYS_STA05	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x001c)
#define STX7200_SYSCONF_SYS_STA06	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0020)
#define STX7200_SYSCONF_SYS_STA07	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0024)
#define STX7200_SYSCONF_SYS_STA08	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0028)
#define STX7200_SYSCONF_SYS_STA09	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x002c)
#define STX7200_SYSCONF_SYS_STA10	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0030)
#define STX7200_SYSCONF_SYS_STA11	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0034)
#define STX7200_SYSCONF_SYS_STA12	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0038)
#define STX7200_SYSCONF_SYS_STA13	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x003c)
#define STX7200_SYSCONF_SYS_STA14	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0040)
#define STX7200_SYSCONF_SYS_STA15	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0044)
#define STX7200_SYSCONF_SYS_CFG00	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0100)
#define STX7200_SYSCONF_SYS_CFG01	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0104)
#define STX7200_SYSCONF_SYS_CFG02	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0108)
#define STX7200_SYSCONF_SYS_CFG03	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x010c)
#define STX7200_SYSCONF_SYS_CFG04	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0110)
#define STX7200_SYSCONF_SYS_CFG05	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0114)
#define STX7200_SYSCONF_SYS_CFG06	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0118)
#define STX7200_SYSCONF_SYS_CFG07	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x011c)
#define STX7200_SYSCONF_SYS_CFG08	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0120)
#define STX7200_SYSCONF_SYS_CFG09	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0124)
#define STX7200_SYSCONF_SYS_CFG10	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0128)
#define STX7200_SYSCONF_SYS_CFG11	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x012c)
#define STX7200_SYSCONF_SYS_CFG12	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0130)
#define STX7200_SYSCONF_SYS_CFG13	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0134)
#define STX7200_SYSCONF_SYS_CFG14	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0138)
#define STX7200_SYSCONF_SYS_CFG15	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x013c)
#define STX7200_SYSCONF_SYS_CFG16	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0140)
#define STX7200_SYSCONF_SYS_CFG17	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0144)
#define STX7200_SYSCONF_SYS_CFG18	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0148)
#define STX7200_SYSCONF_SYS_CFG19	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x014c)
#define STX7200_SYSCONF_SYS_CFG20	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0150)
#define STX7200_SYSCONF_SYS_CFG21	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0154)
#define STX7200_SYSCONF_SYS_CFG22	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0158)
#define STX7200_SYSCONF_SYS_CFG23	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x015c)
#define STX7200_SYSCONF_SYS_CFG24	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0160)
#define STX7200_SYSCONF_SYS_CFG25	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0164)
#define STX7200_SYSCONF_SYS_CFG26	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0168)
#define STX7200_SYSCONF_SYS_CFG27	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x016c)
#define STX7200_SYSCONF_SYS_CFG28	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0170)
#define STX7200_SYSCONF_SYS_CFG29	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0174)
#define STX7200_SYSCONF_SYS_CFG30	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0178)
#define STX7200_SYSCONF_SYS_CFG31	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x017c)
#define STX7200_SYSCONF_SYS_CFG32	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0180)
#define STX7200_SYSCONF_SYS_CFG33	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0184)
#define STX7200_SYSCONF_SYS_CFG34	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0188)
#define STX7200_SYSCONF_SYS_CFG35	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x018c)
#define STX7200_SYSCONF_SYS_CFG36	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0190)
#define STX7200_SYSCONF_SYS_CFG37	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0194)
#define STX7200_SYSCONF_SYS_CFG38	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x0198)
#define STX7200_SYSCONF_SYS_CFG39	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x019c)
#define STX7200_SYSCONF_SYS_CFG40	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01a0)
#define STX7200_SYSCONF_SYS_CFG41	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01a4)
#define STX7200_SYSCONF_SYS_CFG42	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01a8)
#define STX7200_SYSCONF_SYS_CFG43	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01ac)
#define STX7200_SYSCONF_SYS_CFG44	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01b0)
#define STX7200_SYSCONF_SYS_CFG45	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01b4)
#define STX7200_SYSCONF_SYS_CFG46	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01b8)
#define STX7200_SYSCONF_SYS_CFG47	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01bc)
#define STX7200_SYSCONF_SYS_CFG48	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01c0)
#define STX7200_SYSCONF_SYS_CFG49	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01c4)
#define STX7200_SYSCONF_SYS_CFG50	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01c8)
#define STX7200_SYSCONF_SYS_CFG51	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01cc)
#define STX7200_SYSCONF_SYS_CFG52	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01d0)
#define STX7200_SYSCONF_SYS_CFG53	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01d4)
#define STX7200_SYSCONF_SYS_CFG54	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01d8)
#define STX7200_SYSCONF_SYS_CFG55	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01dc)
#define STX7200_SYSCONF_SYS_CFG56	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01e0)
#define STX7200_SYSCONF_SYS_CFG57	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01e4)
#define STX7200_SYSCONF_SYS_CFG58	SH4_DWORD_REG(STX7200_SYSCONF_REGS_BASE + 0x01e8)

#define STX7200_DEVID_7200c1_VAL	0x2C0	/* STx7200 cut 1.x */
#define STX7200_DEVID_7200c2_VAL	0x037	/* STx7200 cut 2.x */
#define STX7200_DEVID_ID_SHIFT		12
#define STX7200_DEVID_ID_MASK		0x3ff	/* ten bits */
#define STX7200_DEVID_CUT_SHIFT		28
#define STX7200_DEVID_CUT_MASK		0xf	/* four bits */

#define STX7200_DEVICEID_7200(ID)	(	\
	((((ID)>>STX7200_DEVID_ID_SHIFT)&STX7200_DEVID_ID_MASK)==STX7200_DEVID_7200c1_VAL)  || \
	((((ID)>>STX7200_DEVID_ID_SHIFT)&STX7200_DEVID_ID_MASK)==STX7200_DEVID_7200c2_VAL)     )
#define STX7200_DEVICEID_CUT(ID)  ((((ID) >> STX7200_DEVID_CUT_SHIFT) & STX7200_DEVID_CUT_MASK) + 1)

#endif /* __STX7200REG_H */
